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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 19-4968; rev 3; 1/11 typical applications circuit appears at end of data sheet. general description the MAX9259/max9260 chipset presents maxims gigabit multimedia serial link (gmsl) technology. the MAX9259 serializer pairs with the max9260 deserializer to form a complete digital serial link for joint transmission of high-speed video, audio, and control data. the MAX9259/max9260 allow a maximum serial payload data rate of 2.5gbps for a 15m shielded twisted-pair (stp) cable. the 24-bit or 32-bit width parallel interface operates up to a maximum bus clock of 104mhz or 78mhz, respectively. this serial link supports display panels from qvga (320 x 240) up to xga (1280 x 768), or dual-view wvga (2 x 854 x 480). the 24-bit or 32-bit mode handles 21 or 29 bits of data, along with an i 2 s input, supporting 4- to 32-bit audio word lengths and an 8khz to 192khz sample rate. the embedded control channel forms a full-duplex, differen - tial 100kbps to 1mbps uart link between the serializer and deserializer. the host electronic control unit (ecu) or microcontroller ( f c) resides either on the MAX9259 (for video display) or on the max9260 (for image sens - ing). in addition, the control channel enables ecu/ f c control of peripherals in the remote side of the serial link through i 2 c (base mode) or a user-defined full-duplex uart format (bypass mode). the MAX9259 serializer driver preemphasis and chan - nel equalizer on the max9260 extend the link length and enhance the link reliability. spread spectrum is available on the MAX9259/max9260 to reduce emi on the serial and parallel output data signals. the differential link complies with the iso 10605 and iec 61000-4-2 esd- protection standards. the core supplies for the MAX9259/max9260 are 1.8v and 3.3v, respectively. both devices use an i/o sup - ply from 1.8v to 3.3v. these devices are available in a 64-pin tqfp package (10mm x 10mm) and a 56-pin tqfn package (8mm x 8mm x 0.75mm) with an exposed pad. electrical performance is guaranteed over the -40 n c to +105 n c automotive temperature range. applications high-speed serial-data transmission for display high-speed serial-data transmission for image sensing automotive navigation, infotainment, and image- sensing systems features s 2.5gbps payload rate, ac-coupled serial link with 8b/10b line coding s 24-bit or 32-bit programmable parallel input bus supports up to xga (1280 x 768) or dual-view wvga (2 x 854 x 480) panels with 18-bit or 24-bit color s 8.33mhz to 104mhz (24-bit bus) or 6.25mhz to 78mhz (32-bit bus) parallel data rate s support two/three 10-bit camera links at 104mhz/78mhz maximum pixel clock s 4-bit to 32-bit word length, 8khz to 192khz i 2 s audio channel supports high-definition audio s embedded half-/full-duplex bidirectional control channel (100kbps to 1mbps) s separate interrupt signal supports touch-screen functions for display panels s remote-end i 2 c master for peripherals s preemphasis line driver (MAX9259)/line equalizer (max9260) s programmable spread spectrum on the serial or parallel data outputs reduce emi s deserializer does not require an external clock s auto data-rate detection allows on-the-fly data-rate change s input clock pll jitter attenuator (MAX9259) s built-in prbs generator/checker for ber testing s line-fault detector detects wire shorts to ground, battery, or open link s iso 10605 and iec 61000-4-2 esd protection s -40 n c to +105 n c operating temperature range s patent pending ordering information /v denotes an automotive qualified part. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. t = tape and reel. evaluation kit available part temp range pin-package MAX9259 gcb/v+ -40 n c to +105 n c 64 tqfp-ep* MAX9259gcb/v+t -40 n c to +105 n c 64 tqfp-ep* MAX9259gtn/v+t -40 n c to +105 n c 56 tqfn-ep* max9260 gcb/v+ -40 n c to +105 n c 64 tqfp-ep* max9260gcb/v+t -40 n c to +105 n c 64 tqfp-ep* www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 2 ______________________________________________________________________________________ stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. avdd to agnd MAX9259 ........................................................... -0.5v to +1.9v max9260 ........................................................... -0.5v to +3.9v dvdd to gnd (MAX9259) ................................... -0.5v to +1.9v dvdd to dgnd (max9260) ................................. -0.5v to +3.9v iovdd to gnd (MAX9259) .................................. -0.5v to +3.9v iovdd to iognd (max9260) .............................. -0.5v to +3.9v any ground to any ground ................................. -0.5v to +0.5v out+, out- to agnd (MAX9259) ...................... -0.5v to +1.9v in+, in- to agnd (max9260) .............................. -0.5v to +1.9v lmn_ to gnd (MAX9259) (60k i source impedance) ................................ -0.5v to +3.9v all other pins to gnd (MAX9259) ....... -0.5v to (iovdd + 0.5v) all other pins to iognd (max9260) ... -0.5v to (iovdd + 0.5v) out+, out- short circuit to ground or supply (MAX9259) ................................................. continuous in+, in- short circuit to ground or supply (max9260) ................................................. continuous continuous power dissipation (t a = +70 n c) 64-pin tqfp (derate 31.3mw/ n c above +70 n c) ....... 2508mw 56-pin tqfn (derate 47.6mw/ n c above +70 n c) .... 3809.5mw esd protection human body model (r d = 1.5k i , c s = 100pf) (out+, out-) to agnd (MAX9259) ............................ q 8kv (in+, in-) to agnd (max9260) .................................... q 8kv all other pins to any ground (MAX9259) .................... q 4kv all other pins to any ground (max9260) .................... q 4kv iec 61000-4-2 (r d = 330 i , c s = 150pf) contact discharge (out+, out-) to agnd (MAX9259) .......................... q 10kv (in+, in-) to agnd (max9260) .................................... q 8kv air discharge (out+, out-) to agnd (MAX9259) .......................... q 12kv (in+, in-) to agnd (max9260) .................................. q 10kv iso 10605 (r d = 2k i , c s = 330pf) contact discharge (out+, out-) to agnd (MAX9259) .......................... q 10kv (in+, in-) to agnd (max9260) .................................... q 8kv air discharge (out+, out-) to agnd (MAX9259) .......................... q 25kv (in+, in-) to agnd (max9260) .................................. q 20kv operating temperature range ........................ -40 n c to +105 n c junction temperature ..................................................... +150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c MAX9259 dc electrical characteristics (v dvdd = v avdd = 1.7v to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 i q 1% (differential), t a = -40 n c to +105 n c, unless otherwise noted. typical values are at v dvdd = v avdd = v iovdd = 1.8v, t a = +25 n c.) absolute maximum ratings 64 tqfp junction-to-ambient thermal resistance ( b ja ) ....... 31.9 n c/w junction-to-case thermal resistance ( b jc ) ................. 1 n c/w 56 tqfn junction-to-ambient thermal resistance ( b ja ) .......... 21 n c/w junction-to-case thermal resistance ( b jc ) ................. 1 n c/w package thermal characteristics (note 1) note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . parameter symbol conditions min typ max units single-ended inputs (din_, pclkin, pwdn , ssen, bws, es, drs, ms, cds, autos , sd, sck, ws) high-level input voltage v ih1 0.65 x v iovdd v low-level input voltage v il1 0.35 x v iovdd v input current i in1 v in = 0 to v iovdd -10 +10 f a input clamp voltage v cl i cl = -18ma -1.5 v single-ended output (int) high-level output voltage v oh1 i oh = -2ma v iovdd - 0.2 v low-level output voltage v ol1 i ol = 2ma 0.2 v output short-circuit current i os v o = 0v v iovdd = 3.0v to 3.6v 16 35 64 ma v iovdd = 1.7v to 1.9v 3 12 21 www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 _______________________________________________________________________________________ 3 MAX9259 dc electrical characteristics (continued) (v dvdd = v avdd = 1.7v to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 i q 1% (differential), t a = -40 n c to +105 n c, unless otherwise noted. typical values are at v dvdd = v avdd = v iovdd = 1.8v, t a = +25 n c.) parameter symbol conditions min typ max units i 2 c and uart i/o, open-drain outputs (rx/sda, tx/scl, lflt ) high-level input voltage v ih2 0.7 x v iovdd v low-level input voltage v il2 0.3 x v iovdd v input current i in2 v in = 0 to v iovdd (note 2) -110 +5 f a low-level open-drain output voltage v ol2 i ol = 3ma v iovdd = 1.7v to 1.9v 0.4 v v iovdd = 3.0v to 3.6v 0.3 differential output (out+, out-) differential output voltage v od preemphasis off (figure 1) 300 400 500 mv p-p 3.3db preemphasis setting, v od(p) (figure 2) 350 610 3.3db deemphasis setting, v od(d) (figure 2) 240 425 change in v od between complementary output states d v od 15 mv output offset voltage, (v out + + v out -)/2 = v os v os preemphasis off 1.1 1.4 1.56 v change in v os between complementary output states d v os 15 mv output short-circuit current i os v out+ or v out- = 0v -60 ma v out+ or v out- = 1.9v 25 magnitude of differential output short-circuit current i osd v od = 0v 25 ma output termination resistance (internal) r o from out+, out- to v avdd 45 54 63 i reverse control-channel receiver (out+, out-) high switching threshold v chr 27 mv low switching threshold v clr -27 mv line-fault-detection input (lmn_) short-to-gnd threshold v tg figure 3 0.3 v normal thresholds v tn figure 3 0.57 1.07 v open thresholds v to figure 3 1.45 v io + 0.06 v open input voltage v io figure 3 1.47 1.75 v short-to-battery threshold v te figure 3 2.47 v power supply worst-case supply current (figure 4) i wcs bws = gnd f pclkin = 16.6mhz 100 125 ma f pclkin = 33.3mhz 105 145 f pclkin = 66.6mhz 116 155 f pclkin = 104mhz 135 175 sleep-mode supply current i ccs 40 110 f a power-down supply current i ccz pwdn = gnd 5 70 f a www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 4 ______________________________________________________________________________________ MAX9259 ac electrical characteristics (v dvdd = v avdd = 1.7v to 1.9v, v iovdd = 1.7v to 3.6v, r l = 100 i q 1% (differential), t a = -40 n c to +105 n c, unless otherwise noted. typical values are at v dvdd = v avdd = v iovdd = 1.8v, t a = +25 n c.) parameter symbol conditions min typ max units parallel clock input (pclkin) clock frequency f pclkin v bws = v gnd , v drs = v iovdd 8.33 16.66 mhz v bws = v gnd , v drs = v gnd 16.66 104 v bws = v iovdd , v drs = v iovdd 6.25 12.5 v bws = v iovdd , v drs = v gnd 12.5 78 clock duty cycle dc t high /t t or t low /t t (figure 5) 35 50 65 % clock transition time t r , t f (figure 5) 4 ns clock jitter t j 3.125gbps, 300khz sinusoidal jitter 800 ps (p-p) i 2 c/uart port timing (note 3) output rise time t r 30% to 70%, c l = 10pf to 100pf, 1k i pullup to iovdd 20 150 ns output fall time t f 70% to 30%, c l = 10pf to 100pf, 1k i pullup to iovdd 20 150 ns input setup time t set i 2 c only (figure 6) 100 ns input hold time t hold i 2 c only (figure 6) 0 ns switching characteristics (note 3) differential output rise-and-fall time t r , t f 20% to 80%, v od 400mv, r l = 100 i , serial-data rate = 3.125gbps 90 150 ps total serial output jitter t tsoj1 3.125gbps prbs signal, measured at v od = 0v differential, preemphasis disabled (figure 7) 0.25 ui deterministic serial output jitter t dsoj2 3.125gbps prbs signal 0.15 ui parallel data input setup time t set (figure 8) 1 ns parallel data input hold time t hold (figure 8) 1.5 ns serializer delay (note 4) t sd (figure 9) spread spectrum enabled 2830 bits spread spectrum disabled 270 link start time t lock (figure 10) 3.5 ms power-up time t pu (figure 11) 3.5 ms i 2 s input timing ws frequency f ws (table 4) 8 192 khz sample word length n ws (table 4) 4 32 bits sck frequency f sck f sck = f ws x n ws x 2 (8 x 4) x 2 (192 x 32) x 2 khz sck clock high time (note 3) t hc v sck v ih , t sck = 1/f sck 0.35 x t sck ns sck clock low time (note 3) t lc v sck v il , t sck = 1/f sck 0.35 x t sck ns sd, ws setup time t set (figure 12, note 3) 2 ns sd, ws hold time t hold (figure 12, note 3) 2 ns www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 _______________________________________________________________________________________ 5 max9260 dc electrical characteristics (v dvdd = v avdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 i q 1% (differential), t a = -40 n c to +105 n c, unless otherwise noted. typical values are at v dvdd = v avdd = v iovdd = 3.3v, t a = +25 n c.) parameter symbol conditions min typ max units single-ended inputs ( enable , int, pwdn , ssen, bws, es, drs, ms, cds, eqs, dcs) high-level input voltage v ih1 0.65 x v iovdd v low-level input voltage v il1 0.35 x v iovdd v input current i in1 v in = 0 to v iovdd -10 +10 f a input clamp voltage v cl i cl = -18ma -1.5 v single-ended outputs (dout_, sd, ws, sck, pclkout) high-level output voltage v oh i oh = -2ma v dcs = v iognd v iovdd - 0.3 v v dcs = v iovdd v iovdd - 0.2 low-level output voltage v ol1 i ol = 2ma v dcs = v iognd 0.3 v v dcs = v iovdd 0.2 output short-circuit current i os dout_, sd, ws, sck v o = 0v, v dcs = v iognd v iovdd = 3.0v to 3.6v 15 25 39 ma v iovdd = 1.7v to 1.9v 3 7 13 v o = 0v, v dcs = v iovdd v iovdd = 3.0v to 3.6v 20 35 63 v iovdd = 1.7v to 1.9v 5 10 21 pclkout v o = 0v, v dcs = v iognd v iovdd = 3.0v to 3.6v 15 33 50 v iovdd = 1.7v to 1.9v 5 10 17 v o = 0v, v dcs = v iovdd v iovdd = 3.0v to 3.6v 30 54 97 v iovdd = 1.7v to 1.9v 9 16 32 i 2 c and uart i/o, open-drain outputs (rx/sda, tx/scl, err , gpio_, lock) high-level input voltage v ih2 0.7 x v iovdd v low-level input voltage v il2 0.3 x v iovdd v input current i in2 v in = 0 to v iovdd (note 2) rx/sda, tx/scl -110 +1 f a gpio, err , lock -80 +1 low-level open-drain output voltage v ol2 i ol = 3ma v iovdd = 1.7v to 1.9v 0.4 v v iovdd = 3.0v to 3.6v 0.3 v www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 6 ______________________________________________________________________________________ max9260 dc electrical characteristics (continued) (v dvdd = v avdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 i q 1% (differential), t a = -40 n c to +105 n c, unless otherwise noted. typical values are at v dvdd = v avdd = v iovdd = 3.3v, t a = +25 n c.) parameter symbol conditions min typ max units differential outputs for reverse control channel (in+, in-) differential high output peak voltage, (v in +) - (v in -) v roh no high-speed data transmission (figure 13) 30 60 mv differential low output peak voltage, (v in +) - (v in -) v rol no high-speed data transmission (figure 13) -60 -30 mv differential inputs (in+, in-) differential high input threshold (peak), (v in +) - (v in -) v idh(p) (figure 14) 40 90 mv differential low input threshold (peak), (v in +) - (v in -) v idl(p) (figure 14) -90 -40 mv input common-mode voltage, ((v in +) + (v in -))/2 v cmr 1 1.3 1.6 v differential input resistance (internal) r i 80 100 130 i power supply worst-case supply current (figure 15) i wcs v bws = v iognd , f pclkout = 16.6mhz 2% spread spectrum active 113 166 ma spread spectrum disabled 105 155 v bws = v iognd , f pclkout = 33.3mhz 2% spread spectrum active 122 181 spread spectrum disabled 110 165 v bws = v iognd , f pclkout = 66.6mhz 2% spread spectrum active 137 211 spread spectrum disabled 120 188 v bws = v iognd , f pclkout = 104mhz 2% spread spectrum active 159 247 spread spectrum disabled 135 214 sleep-mode supply current i ccs 80 130 f a power-down supply current i ccz v pwdn = v iognd 19 70 f a www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 _______________________________________________________________________________________ 7 max9260 ac electrical characteristics (v dvdd = v avdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 i q 1% (differential), t a = -40 n c to +105 n c, unless otherwise noted. typical values are at v dvdd = v avdd = v iovdd = 3.3v, t a = +25 n c.) parameter symbol conditions min typ max units parallel clock output (pclkout) clock frequency f pclkout v bws = v iognd , v drs = v iovdd 8.33 16.66 mhz v bws = v iognd , v drs = v iognd 16.66 104 v bws = v iovdd , v drs = v iovdd 6.25 12.5 v bws = v iovdd , v drs = v iognd 12.5 78 clock duty cycle dc t high /t t or t low /t t (figure 16) 40 50 60 % clock jitter t j period jitter, rms, spread off, 3.125gbps, prbs pattern, ui = 1/f pclkout 0.05 ui i 2 c/uart port timing output rise time t r 30% to 70%, c l = 10pf to 100pf, 1k i pullup to iovdd 20 150 ns output fall time t f 70% to 30%, c l = 10pf to 100pf, 1k i pullup to iovdd 20 150 ns input setup time t set i 2 c only 100 ns input hold time t hold i 2 c only 0 ns switching characteristics pclkout rise-and-fall time t r , t f 20% to 80%, v iovdd = 1.7v to 1.9v v dcs = v iovdd , c l = 10pf 0.4 2.2 ns v dcs = v iognd , c l = 5pf 0.5 2.8 20% to 80%, v iovdd = 3.0v to 3.6v v dcs = v iovdd , c l = 10pf 0.25 1.7 v dcs = v iognd , c l = 5pf 0.3 2.0 parallel data rise-and-fall time (figure 17) t r , t f 20% to 80%, v iovdd = 1.7v to 1.9v v dcs = v iovdd , c l = 10pf 0.5 3.1 ns v dcs = v iognd , c l = 5pf 0.6 3.8 20% to 80%, v iovdd = 3.0v to 3.6v v dcs = v iovdd , c l = 10pf 0.3 2.2 v dcs = v iognd , c l = 5pf 0.4 2.4 deserializer delay t sd spread spectrum enabled (figure 18) 2880 bits spread spectrum disabled (figure 18) 750 lock time t lock spread spectrum enabled (figure 19) 1500 f s spread spectrum off (figure 19) 1000 power-up time t pu (figure 20) 2500 f s reverse control-channel output rise time t r no high-speed transmission (figure 13) 180 400 ns reverse control-channel output fall time t f no high-speed transmission (figure 13) 180 400 ns www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 8 ______________________________________________________________________________________ typical operating characteristics (v dvdd = v avdd = v iovdd = 1.8v (MAX9259), v dvdd = v avdd = v iovdd = 3.3v (max9260), t a = +25 n c, unless otherwise noted.) max9260 ac electrical characteristics (continued) (v dvdd = v avdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 i q 1% (differential), t a = -40 n c to +105 n c, unless otherwise noted. typical values are at v dvdd = v avdd = v iovdd = 3.3v, t a = +25 n c.) note 2: minimum i in due to voltage drop across the internal pullup resistor. note 3: not production tested. note 4: bit time = 1/(30 x f rxclkin ) (bws = 0), = 1/(40 x f rxclkin ) (bws = v iovdd ). note 5: rising to rising edge jitter can be twice as large. parameter symbol conditions min typ max units i 2 s output timing ws jitter t aj-ws t ws = 1/f ws , rising (falling) edge to falling (rising) edge (note 5) f ws = 48khz or 44.1khz 0.4e - 3 x t ws 0.5e - 3 x t ws ns f ws = 96khz 0.8e - 3 x t ws 1e - 3 x t ws f ws = 192khz 1.6e - 3 x t ws 2e - 3 x t ws sck jitter t aj-sck t sck = 1/f sck , rising edge to rising edge n ws = 16 bits, f ws = 48khz or 44.1khz 13e - 3 x t sck 16e - 3 x t sck ns n ws = 24 bits, f ws = 96khz 39e - 3 x t sck 48e - 3 x t sck n ws = 32 bits, f ws = 192khz 0.1 x t sck 0.13 x t sck audio skew relative to video ask video and audio synchronized 3 x t ws 4 x t ws s sck, sd, ws rise-and-fall time t r , t f 20% to 80% v dcs = v iovdd , c l = 10pf 0.3 3.1 ns v dcs = v iognd , c l = 5pf 0.4 3.8 ns sd, ws valid time before sck t dvb t sck = 1/f sck (figure 21) 0.35 x t sck 0.5 x t sck ns sd, ws valid time after sck t dva t sck = 1/f sck (figure 21) 0.35 x t sck 0.5 x t sck ns MAX9259 supply current vs. pclkin frequency (24-bit mode) MAX9259/60 toc01 pclkin frequency (mhz) supply current (ma) 85 65 45 25 95 100 105 110 115 120 125 130 135 90 5 105 preemphasis = 0x0b to 0x0f preemphasis = 0x01 to 0x04 preemphasis = 0x00 MAX9259 supply current vs. pclkin frequency (32-bit mode) MAX9259/60 toc02 pclkin frequency (mhz) supply current (ma) 65 50 35 20 95 100 105 110 115 120 125 130 135 90 5 80 preemphasis = 0x0b to 0x0f preemphasis = 0x01 to 0x04 preemphasis = 0x00 max9260 supply current vs. pclkout frequency (24-bit mode) pclkout frequency (mhz) supply current (ma) 85 65 45 25 110 115 120 125 130 135 140 145 150 155 105 5 105 MAX9259/60 toc03 all equalizer settings www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 _______________________________________________________________________________________ 9 typical operating characteristics (continued) (v dvdd = v avdd = v iovdd = 1.8v (MAX9259), v dvdd = v avdd = v iovdd = 3.3v (max9260), t a = +25 n c, unless otherwise noted.) maximum pclkin frequency vs. stp cable length (ber < 10 -9 ) cable length (m) frequency (mhz) 15 10 5 20 40 60 80 100 120 0 0 20 MAX9259/60 toc12 optimum pe/eq settings ber can be < 10 -12 for cable lengths less than 10m no pe, eqs = low no pe, eqs = high output power spectrum vs. pclkout frequency (max9260 spread on, MAX9259 spread off) pclkout frequency (mhz) pclkout output power (dbm) 44 43 40 41 42 -70 -60 -50 -40 -30 -20 -10 0 -80 39 45 MAX9259/60 toc11 0% spread 4% spread 2% spread f pclkout = 42mhz output power spectrum vs. pclkout frequency (MAX9259 spread on, max9260 spread off) pclkout frequency (mhz) pclkout output power (dbm) 44 43 40 41 42 -70 -60 -50 -40 -30 -20 -10 0 -80 39 45 MAX9259/60 toc10 0% spread 0.5% spread 4% spread 2% spread f pclkout = 42mhz output power spectrum vs. pclkout frequency (MAX9259 spread on, max9260 spread off) pclkout frequency (mhz) pclkout output power (dbm) 21.0 20.5 19.0 19.5 20.0 -70 -60 -50 -40 -30 -20 -10 0 -80 18.5 21.5 MAX9259/60 toc09 0% spread 0.5% spread 4% spread 2% spread f pclkout = 20mhz serial link switching pattern with 14db preemphasis (parallel bit rate = 104mhz, 10m stp cable) MAX9259/60 toc08 250.0mv -250.0mv 52.00ps/div 3.12gbps serial link switching pattern without preemphasis (parallel bit rate = 104mhz, 10m stp cable) MAX9259/60 toc07 400.0mv 3.12gbps -400.0mv 52.00ps/div max9260 supply current vs. pclkout frequency (32-bit mode) pclkout frequency (mhz) supply current (ma) 65 50 20 35 110 120 130 140 160 150 170 180 100 5 80 MAX9259/60 toc06 2%, 4% spread no spread max9260 supply current vs. pclkout frequency (24-bit mode) pclkout frequency (mhz) supply current (ma) 85 65 25 45 110 120 130 140 160 150 170 180 100 5 105 MAX9259/60 toc05 2%, 4% spread no spread max9260 supply current vs. pclkout frequency (32-bit mode) pclkout frequency (mhz) supply current (ma) 65 50 35 20 110 115 120 125 130 135 140 145 150 155 105 5 80 MAX9259/60 toc04 all equalizer settings www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 10 _____________________________________________________________________________________ pin configurations 58 59 60 61 62 54 55 56 57 63 38 39 40 41 42 43 44 45 46 47 din8 din14 es top view drs int lmn0 avdd out+ out- agnd lmn1 52 53 49 50 51 ssen tx/scl rx/sda pwdn cds din13 din16 din15 iovdd pclkin agnd gnd din17 avdd din19 din18 din21 din20 din22 gnd iovdd autos ws sck sd din28 din27 din26 din25 33 34 35 36 37 din24 gnd dvdd agnd din23 din7 din6 din5 din4 din3 din11 din10 dvdd gnd din9 din2 din1 iovdd gnd 48 ms din0 64 bws din12 23 22 21 20 19 27 26 25 24 18 29 28 32 31 30 17 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 MAX9259 MAX9259 lflt ep* tqfp (10mm 10mm 1mm) 58 59 60 61 62 54 55 56 57 63 38 39 40 41 42 43 44 45 46 47 dout0 int dout10 tqfp (10mm 10mm 1mm) top view dout11 dout12 dout14 dout15 pclkout dout16 dout17 dout18 52 53 49 50 51 dout19 dout20 dout21 dout22 dout23 bws gpio0 cds avdd es in- in+ eqs agnd dcs gpio1 dvdd ms dgnd iognd iovdd dout25 dout26 dout27 dout28/mclk sd sck ws lock 33 34 35 36 37 iognd err pwdn tx/scl rx/sda dout1 dout2 dout3 dout4 dout5 agnd avdd drs ssen iognd dout6 dout7 iovdd iognd 48 dout24 dout8 64 dout9 enable 23 22 21 20 19 27 26 25 24 18 29 28 32 31 30 17 max9260 dout13 ep* ep* 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 top view tqfn (8mm x 8mm x 0.75mm) 15 17 16 18 19 20 21 22 23 24 25 26 27 28 din23 dvdd din24 din25 din26 din27 din28 sd sck ws autos iovdd ms cds din11 din10 dvdd din9 din8 din7 din6 din5 din4 din3 din2 din1 iovdd din0 *connect ep to ground plane 48 47 46 45 44 43 54 53 56 55 52 51 50 49 1 2 + 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 42 41 40 39 38 37 36 35 34 33 32 31 30 29 din20 din21 din22 din19 din18 din17 avdd iovdd pclkin din16 din15 din14 din13 din12 tx/scl rx/sda pwdn ssen lmn1 out- out+ avdd lmn0 lflt int drs es bws www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 ______________________________________________________________________________________ 11 MAX9259 pin description pin name function tqfp tqfn 1C5, 11C17, 21C25, 49, 52C60, 63, 64 1C5, 9C15, 17C21, 43, 45C53, 55, 56 din0C din28 data input[0:28]. parallel data inputs. all pins internally pulled down to gnd. selected edge of pclkin latches input data. set bws = low (24-bit mode) to use din0Cdin20 (rgb and sync). din21Cdin28 are not used in 24-bit mode. set bws = high (32-bit mode) to use din0Cdin28 (rgb, sync, and two extra inputs). 6 6 pclkin parallel clock input. latches parallel data inputs and provides the pll reference clock. 7, 30, 51 7, 26, 44 iovdd i/o supply voltage. 1.8v to 3.3v logic i/o power supply. bypass iovdd to gnd with 0.1 f f and 0.001 f f capacitors as close as possible to the device with the smaller value capacitor closest to iovdd. 8, 20, 31, 50, 61 gnd digital and i/o ground 9, 18, 39 agnd analog ground 10, 42 8, 36 avdd 1.8v analog power supply. bypass avdd to agnd with 0.1 f f and 0.001 f f capacitors as close as possible to the device with the smaller value capacitor closest to avdd. 19, 62 16, 54 dvdd 1.8v digital power supply. bypass dvdd to gnd with 0.1 f f and 0.001 f f capacitors as close as possible to the device with the smaller value capacitor closest to dvdd. 26 22 sd i 2 s serial-data input with internal pulldown to gnd. disable i 2 s to use sd as an additional data input latched on the selected edge of pclkin. 27 23 sck i 2 s serial-clock input with internal pulldown to gnd 28 24 ws i 2 s word-select input with internal pulldown to gnd 29 25 autos autostart setting. active-low power-up mode selection input requires external pulldown or pullup resistors. set autos = high to power up the device with no link active. set autos = low to have the MAX9259 power up the serial link with autorange detection (see tables 13 and 14). 32 27 ms mode select. control-link mode-selection input requires external pulldown or pullup resistors. set ms = low, to select base mode. set ms = high to select the bypass mode. 33 28 cds control-direction selection. control-link-direction selection input requires external pulldown or pullup resistors. set cds = low for f c use on the MAX9259 side of the serial link. set cds = high for f c use on the max9260 side of the serial link. 34 29 pwdn power-down. active-low power-down input requires external pulldown or pullup resistors. 35 30 rx/sda receive/serial data. uart receive or i 2 c serial-data input/output with internal 30k i pullup to iovdd. in uart mode, rx/sda is the rx input of the MAX9259s uart. in i 2 c mode, rx/sda is the sda input/output of the MAX9259s i 2 c master. www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 12 _____________________________________________________________________________________ MAX9259 pin description (continued) pin name function tqfp tqfn 36 31 tx/scl transmit/serial clock. uart transmit or i 2 c serial-clock output with internal 30k i pullup to iovdd. in uart mode, tx/scl is the tx output of the MAX9259s uart. in i 2 c mode, tx/scl is the scl output of the MAX9259s i 2 c master. 37 32 ssen spread-spectrum enable. serial link spread-spectrum enable input requires external pulldown or pullup resistors. the state of ssen latches upon power-up or when resuming from power-down mode ( pwdn = low). set ssen = high for q 0.5% spread spectrum on the serial link. set ssen = low to use the serial link without spread spectrum. 38 33 lmn1 line-fault monitor input 1 (see figure 3 for details) 40, 41 34, 35 out-, out+ differential cml output -/+ . differential outputs of the serial link. 43 37 lmn0 line-fault monitor input 0 (see figure 3 for details) 44 38 lflt line fault. active-low open-drain line-fault output with a 60k i internal pullup resistor. lflt = low indicates a line fault. lflt is high impedance when pwdn = low. 45 39 int interrupt output to indicate remote side requests. int = low upon power-up and when pwdn = low. a transition on the int input of the max9260 toggles the MAX9259s int output. 46 40 drs data-rate select. data-rate range-selection input requires external pulldown or pullup resistors. set drs = high for parallel input data rates of 8.33mhz to 16.66mhz (24-bit mode) or 6.25mhz to 12.5mhz (32-bit mode). set drs = low for parallel input data rates of 16.66mhz to 104mhz (24-bit mode) or 12.5mhz to 78mhz (32-bit mode). 47 41 es edge select. pclkin trigger edge-selection input requires external pulldown or pullup resistors. set es = low to trigger on the rising edge of pclkin. set es = high to trigger on the falling edge of pclkin. 48 42 bws bus-width select. parallel input bus-width selection input requires external pulldown or pullup resistors. set bws = low for 24-bit bus mode. set bws = high for 32-bit bus mode. ep exposed pad. ep internally connected to agnd (tqfp package) or agnd and gnd (tqfn package). must externally connect ep to the agnd plane to maximize thermal and electrical performance. www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 ______________________________________________________________________________________ 13 max9260 pin description pin name function 1 enable enable. active-low parallel output-enable input requires external pulldown or pullup resistors. set enable = low to enable pclkout, sd, sck, ws, and the parallel out - puts, dout_. set enable = high to put pclkout, sd, sck, ws, and dout_ to high impedance. 2 bws bus-width select. parallel output bus-width selection input requires external pulldown or pullup resistors. set bws = low for 24-bit bus mode. set bws = high for 32-bit bus mode. 3 int interrupt. interrupt input requires external pulldown or pullup resistors. a transition on the int input of the max9260 toggles the MAX9259s int output. 4 cds control-direction selection. control-link-direction selection input requires external pull - down or pullup resistors. set cds = low for f c use on the MAX9259 side of the serial link. set cds = high for f c use on the max9260 side of the serial link. 5 gpio0 gpio0. open-drain general-purpose input/output with internal 60k i pullup resistors to iovdd. gpio0 is high impedance during power-up and when pwdn = low. 6 es edge select. pclkout edge-selection input requires external pulldown or pullup resistors. set es = low for a rising-edge trigger. set es = high for a falling-edge trigger. 7, 63 avdd 3.3v analog power supply. bypass avdd to agnd with 0.1f and 0.001f capacitors as close as possible to the device with the smallest value capacitor closest to avdd. 8 , 9 in+, in- differential cml input +/- . differential inputs of the serial link. 10, 64 agnd analog ground 11 eqs equalizer select. deserializer equalizer-selection input requires external pulldown or pullup resistors. the state of eqs latches upon power-up or rising edge of pwdn . set eqs = low for 10.7db equalizer boost (eqtune = 1001). set eqs = high for 5.2db equalizer boost (eqtune = 0100). 12 gpio1 gpio1. open-drain general-purpose input/output with internal 60k i pullup resistors to iovdd. gpio1 is high impedance during power-up and when pwdn = low. 13 dcs drive current select. driver current-selection input requires external pulldown or pul - lup resistors. set dcs = high for stronger parallel data and clock output drivers. set dcs = low for normal parallel data and clock drivers (see the max9260 dc electrical characteristics table). 14 ms mode select. control-link mode-selection/autostart mode selection input requires external pulldown or pullup resistors. ms sets the control-link mode when cds = high (see the control-channel and register programming section). set ms = low to select base mode. set ms = high to select the bypass mode. ms sets autostart mode when cds = low (see tables 13 and 14). 15 dvdd 3.3v digital power supply. bypass dvdd to dgnd with 0.1 f f and 0.001 f f capacitors as close as possible to the device with the smaller value capacitor closest to dvdd. 16 dgnd digital ground 17 rx/sda receive/serial data. uart receive or i 2 c serial-data input/output with internal 30k i pullup to iovdd. in uart mode, rx/sda is the rx input of the max9260s uart. in i 2 c mode, rx/sda is the sda input/output of the MAX9259s i 2 c master. www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 14 _____________________________________________________________________________________ max9260 pin description (continued) pin name function 18 tx/scl transmit/serial clock. uart transmit or i 2 c serial-clock output with internal 30k i pullup to iovdd. in uart mode, tx/scl is the tx output of the MAX9259s uart. in i 2 c mode, tx/scl is the scl output of the max9260s i 2 c master. 19 pwdn power-down. active-low power-down input requires external pulldown or pullup resis - tors. 20 err error. active-low open-drain video data error output with internal pullup to iovdd. err goes low when the number of decoding errors during normal operation exceed a programmed error threshold or when at least one prbs error is detected during prbs test. err is high impendence when pwdn = low. 21, 31, 50, 60 iognd input/output ground 22 lock open-drain lock output with internal pullup to iovdd. lock = high indicates plls are locked with correct serial-word-boundary alignment. lock = low indicates plls are not locked or incorrect serial-word-boundary alignment. lock remains low when the configuration link is active. lock is high impedance when pwdn = low. 23 ws word select. i 2 s word-select output. 24 sck serial clock. i 2 s serial-clock output 25 sd serial data. i 2 s serial-data output. disable i 2 s to use sd as an additional data output latched on the selected edge of pclkout. 26C29, 32C40, 42C49, 52C59 dout0C dout27, dout28/mclk data output[0:28]. parallel data outputs. output data can be strobed on the selected edge of pclkout. set bws = low (24-bit mode) to use dout0Cdout20 (rgb and sync). dout21Cdout28 are not used in 24-bit mode and are set to low. set bws = high (32-bit mode) to use dout0Cdout28 (rgb, sync, and two extra outputs). dout28 can be used to output mclk (see the additional mclk output for audio applications section). 30, 51 iovdd 1.8v to 3.3v logic i/o power supply. bypass iovdd to iognd with 0.1 f f and 0.001 f f capacitors as close as possible to the device with the smaller value capacitor closest to iovdd. 41 pclkout parallel clock output. used for dout0Cdout28. 61 ssen spread-spectrum enable. parallel output spread-spectrum enable input requires external pulldown or pullup resistors. the state of ssen latches upon power-up or when resuming from power-down mode ( pwdn = low). set ssen = high for q 2% spread spectrum on the parallel outputs. set ssen = low to use the parallel outputs without spread spectrum. 62 drs data-rate select. data-rate range-selection input requires external pulldown or pullup resistors. set drs = high for parallel input data rates of 8.33mhz to 16.66mhz (24-bit mode) or 6.25mhz to 12.5mhz (32-bit mode). set drs = low for parallel input data rates of 16.66mhz to 104mhz (24-bit mode) or 12.5mhz to 78mhz (32-bit mode). ep exposed pad. ep internally connected to agnd. must externally connect ep to the agnd plane to maximize thermal and electrical performance. www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 ______________________________________________________________________________________ 15 functional diagram filter pll audio fifo prbs gen spread pll line- fault det cml tx p s 8b/10b encode parity fifo din[n:0] ws, sd, sck out+ out- lmn0 lmn1 pclkin tx/scl rx/sda clkdiv uart/i 2 c term rev ch rx lflt spread pll audio fifo prbs check cdr pll eq cml rx p s 8b/10b decode parity fifo dout[n:0] ws, sd, sck in- stp cable (z 0 = 50) in+ pclkout serializer deserializer tx/scl rx/sda clkdiv uart/i 2 c term rev ch tx MAX9259 max9260 www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 16 _____________________________________________________________________________________ figure 1. MAX9259 serial output parameters figure 2. output waveforms at out+ and out- out- v od v os gnd r l /2 r l /2 out+ out- out+ (out+) - (out-) v os(-) v os(+) ((out+) + (out-))/2 v os(-) v od(-) v od(-) v od = 0v dv os = |v os(+) - v os(-) | dv od = |v od(+) - v od(-) | v od (+) out+ out- v os v od(p) v od(d) serial-bit time www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 ______________________________________________________________________________________ 17 figure 3. fault-detector circuit figure 4. MAX9259 worst-case pattern input output logic (out+) 2.1v lflt 1.5v 0.5v reference voltage generator connectors *q1% tolerance output logic (out-) MAX9259 45.3ki* lmn1 lmn0 45.3ki* 1.7v to 1.9v 4.99ki* 49.9ki* 49.9ki* 4.99ki* twisted pair out+ out- pclkin note: pclkin programmed for rising latch edge. din_ www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 18 _____________________________________________________________________________________ figure 5. MAX9259 parallel input clock requirements figure 6. i 2 c timing parameters figure 7. differential output template v il max t high t low t t t r t f v ih min pclkin p t r p s s t hold t f t set tx/ scl rx/ sda 800mv t tsoj1 2 t tsoj1 2 www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 ______________________________________________________________________________________ 19 figure 8. MAX9259 input setup-and-hold times figure 9. MAX9259 serializer delay v ih min v ih min v ih min v il max v il max v il max pclkin din_ t hold t set note: pclkin programmed for rising latching edge. t sd first bit last bit n n+3 expanded time scale n+4 n n+1 n+2 n-1 din_ pclkin out+/- www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 20 _____________________________________________________________________________________ figure 10. MAX9259 link startup time figure 11. MAX9259 power-up delay figure 12. MAX9259 input i 2 s timing parameters serial link inactive serial link active channel disabled reverse control channel disabled t lock 350fs pclkin reverse control channel available pwdn must be high pwdn powered down v ih1 t pu reverse control channel disabled 350s pclkin powered up, serial link inactive powered up, serial link active reverse control channel enabled reverse control channel enabled reverse control channel disabled ws t hold t set t hold t set t hc t sck t lc sck sd www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 ______________________________________________________________________________________ 21 figure 13. max9260 reverse control-channel output parameters figure 14. max9260 test circuit for differential input measurement figure 15. max9260 worst-case pattern output max9260 reverse control-channel transmitter in+ in- in- in+ in+ in- v od r l /2 r l /2 v cmr v cmr v roh (in+) - (in-) t r 0.1 x v rol 0.9 x v rol t f v rol 0.9 x v roh 0.1 x v roh v in+ r l /2 r l /2 c in c in v id(p) in+ in- v id(p) = | v in+ - v in- | v cmr = (v in+ + v in- )/2 v in- _ + _ _ + pclkout dout_ note: pclkout programmed for rising latch edge. www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 22 _____________________________________________________________________________________ figure 16. max9260 clock output high-and-low times figure 17. max9260 output rise-and-fall times figure 18. max9260 deserializer delay v ol max t high t low t t v oh min pclkout 0.8 x v i0vcc 0.2 x v i0vcc t f t r c l single-ended output load max9260 first bit in+/- dout_ pclkout last bit serial word n serial-word length serial word n+1 serial word n+2 t sd parallel word n-2 parallel word n-1 parallel word n note: pclkout programmed for rising latching edge. www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 ______________________________________________________________________________________ 23 figure 19. max9260 lock time figure 20. max9260 power-up delay figure 21. max9260 output i 2 s timing parameters in+ - in- lock t lock pwdn must be high v oh in+/- lock t pu pwdn v oh v ih1 ws t dva t dvb t dva t f t dvb t r sck sd www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 24 _____________________________________________________________________________________ detailed description the MAX9259/max9260 chipset presents maxims gmsl technology. the MAX9259 serializer pairs with the max9260 deserializer to form a complete digital serial link for joint transmission of high-speed video, audio, and control data for video-display or image-sensing applications. the serial-payload data rate can reach up to 2.5gbps for a 15m stp cable. the parallel interface is programmable for 24-bit or 32-bit width modes at the maximum bus clock of 104mhz or 78mhz, respectively. the minimum bus clock is 6.25mhz for the 32-bit mode and 8.33mhz for the 24-bit mode. with such a flexible data configuration, the gmsl is able to support xga (1280 x 768) or dual-view wvga (2 x 854 x 480) display panels. for image sensing, it supports three 10-bit cam - era links simultaneously with a pixel clock up to 78mhz. the 24-bit mode handles 21-bit data and control signals plus an i 2 s audio signal. the 32-bit mode handles 29-bit data and control signals plus an i 2 s audio signal. any combination and sequence of color video data, video sync, and control signals make up the 21-bit or 29-bit parallel data on din_ and dout_. the i 2 s port supports the sampled audio data at a rate from 8khz to 192khz and the audio word length of anywhere between 4 to 32 bits. the embedded control channel forms a uart link between the serializer and deserializer. the uart link can be set to half-duplex mode or full-duplex mode depending on the application. the gmsl supports uart rates from 100kbps to 1mbps. using this control link, a host ecu or f c communicates with the serializer and deserializer, as well as the peripherals in the remote side, such as backlight control, grayscale gamma cor - rection, camera module, and touch screen. all serial communication (forward and reverse) uses differential signaling. the peripheral programming uses i 2 c format or the default gmsl uart format. a separate bypass mode enables communication using a full-duplex, user- defined uart format. the control link between the MAX9259 and max9260 allows f c connectivity to either device or peripherals to support video-display or image- sensing applications. the ac-coupled serial link uses 8b/10b coding. the MAX9259 serializer features a programmable driver preemphasis and the max9260 deserializer features a programmable channel equalizer to extend the link length and enhance the link reliability. both devices have a programmable spread-spectrum feature for reducing emi on the serial link output (MAX9259) and parallel data outputs (max9260). the differential serial link input and output pins comply with the iso 10605 and iec 61000- 4-2 esd-protection standards. the core supplies for the MAX9259/max9260 are 1.8v and 3.3v, respectively. both devices use an i/o supply from 1.8v to 3.3v register mapping the f c configures various operating conditions of the gmsl through registers in the MAX9259/max9260. the default device addresses stored in the r0 and r1 registers of the MAX9259/max9260 are 0x80 and 0x90, respectively. write to the r0/r1 registers in both devices to change the device address of the MAX9259 or max9260. table 1. MAX9259 power-up default register map (see table 18) register address (hex) power-up default (hex) power-up default settings (msb first) 0x00 0x80 serid =1000000, serializer device address is 1000 000 reserved = 0 0x01 0x90 desid =1001000, deserializer device address is 1001 000 reserved = 0 0x02 0x1f, 0x3f ss = 000 (ssen = low), ss = 001 (ssen = high), spread-spectrum settings depend on ssen pin state at power-up audioen = 1, i 2 s channel enabled prng = 11, automatically detect the pixel clock range srng = 11, automatically detect serial-data rate 0x03 0x00 autofm = 00, calibrate spread-modulation rate only once after locking sdiv = 000000, auto calibrate sawtooth divider www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 ______________________________________________________________________________________ 25 table 1. MAX9259 power-up default register map (see table 18) (continued) table 2. max9260 power-up default register map (see table 19) register address (hex) power-up default (hex) power-up default settings (msb first) 0x04 0x03, 0x13, 0x83, or 0x93 seren = 0 ( autos = high), seren = 1 ( autos = low), serial link enable default depends on autos pin state at power-up clinken = 0, configuration link disabled prbsen = 0, prbs test disabled sleep = 0 or 1, sleep mode state depends on cds and autos pin state at power-up (see the link startup procedure section) inttype = 00, base mode uses i 2 c revccen = 1, reverse control channel active (receiving) fwdccen = 1, forward control channel active (sending) 0x05 0x70 i2cmethod = 0, i 2 c packets include register address disfpll = 1, filter pll disabled cmllvl = 11, 400mv cml signal level preemp = 0000, preemphasis disabled 0x06 0x40 reserved = 01000000 0x07 0x22 reserved = 00100010 0x08 0x0a (read only) reserved = 0000 lfneg = 10, no faults detected lfpos = 10, no faults detected 0x0d 0x0f setint = 0, interrupt output set to low reserved = 0001111 0x1e 0x01 (read only) id = 00000001, device id is 0x01 0x1f 0x0x (read only) reserved = 0000 revision = xxxx, revision number register address (hex) power-up default (hex) power-up default settings (msb first) 0x00 0x80 serid =1000000, serializer device identifier is 1000 000 reserved = 0 0x01 0x90 desid =1001000, deserializer device identifier is 1001 000 reserved = 0 0x02 0x1f or 0x5f ss = 00 (ssen = low), ss = 01 (ssen = high), spread-spectrum settings depend on ssen pin state at power-up reserved = 0 audioen = 1, i 2 s channel enabled prng = 11, automatically detect the pixel clock range srng = 11, automatically detect serial-data rate www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 26 _____________________________________________________________________________________ table 2. max9260 power-up default register map (see table 19) (continued) register address (hex) power-up default (hex) power-up default settings (msb first) 0x03 0x00 autofm = 00, calibrate spread-modulation rate only once after locking reserved = 0 sdiv = 00000, autocalibrate sawtooth divider 0x04 0x03, 0x13, 0x83, or 0x93 locked = 0, lock output = low (read only) outenb = 0 ( enable = low), outenb = 1 ( enable = high), outenb default depends on enable pin state at power-up prbsen = 0, prbs test disabled sleep = 0 or 1, sleep setting default depends on cds and ms pin state at pow - er-up (see the link startup procedure section) inttype = 00, base mode uses i 2 c revccen = 1, reverse control channel active (sending) fwdccen = 1, forward control channel active (receiving) 0x05 0x28 or 0x29 reserved = 0 hpftune = 01, 3.75mhz equalizer highpass cutoff frequency pdhf = 0, high-frequency boosting disabled eqtune = 1000 (eqs = high, 10.7db), eqtune = 1001 (eqs = low, 5.2db), eqtune default setting depends on eqs pin state at power-up 0x06 0x0f disstag = 0, staggered outputs enabled autorst = 0, error registers/output auto reset disabled disint = 0, int transmission enabled int = 0, int output = low (read only) gpio1out = 1, gpio1 output set to high gpio1 = 1, gpio1 input = high (read only) gpio0out = 1, gpio0 output set to high gpio0 = 1, gpio0 input = high (read only) 0x07 0x54 reserved = 01010100 0x08 0x30 reserved = 00110000 0x09 0xc8 reserved = 11001000 0x0a 0x12 reserved = 00010010 0x0b 0x20 reserved = 00100000 0x0c 0x00 errthr = 00000000, error threshold set to zero for decoding errors 0x0d 0x00 (read only) decerr = 00000000, zero decoding errors detected 0x0e 0x00 (read only) prbserr = 00000000, zero prbs errors detected 0x12 0x00 mclksrc = 0, mclk is derived from pclkout (see table 5) mclkdiv = 0000000, mclk output is disabled 0x1e 0x02 (read only) id = 00000010, device id is 0x02 0x1f 0x0x (read only) reserved = 0000 revision = xxxx www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 ______________________________________________________________________________________ 27 parallel inputs and outputs the parallel bus uses two selectable bus widths, 24 bits and 32 bits. bws selects the bus width according to table 3. in 24-bit mode, din21Cdin28 are not used and are internally pulled down. for both modes, sd, sck, and ws pins are dedicated for i 2 s audio data. the assignments of the first 21 or 29 signals are interchange - able and appear in the same order at both sides of the serial link. in image-sensing applications, disabling the i 2 s audio channel (through the MAX9259 and max9260 internal registers) allows the MAX9259 to serialize three 10-bit camera data streams through din[0:28] plus sd inputs. the parallel bus accepts data clock rates from 8.33mhz to 104mhz for the 24-bit mode and 6.25mhz to 78mhz for the 32-bit mode. serial link signaling and data format the MAX9259 high-speed data serial output uses cml signaling with programmable preemphasis and ac-coupling. the max9260 high-speed receiver uses ac-coupling and programmable channel equalization. together, the gmsl operates at up to 3.125gbps over stp cable lengths up to 15m. the MAX9259 serializer scrambles and encodes the parallel input bits, and sends the 8b/10b coded sig - nal through the serial link. the max9260 deserializer recovers the embedded serial clock and then samples, decodes, and descrambles the data onto the paral - lel output bus. figures 22 and 23 show the serial-data packet format prior to scrambling and 8b/10b coding. for the 24-bit or 32-bit mode, the first 21 or 29 serial bits come from din[20:0] or din[28:0], respectively. the audio channel bit (acb) contains an encoded audio signal derived from the three i 2 s inputs (sd, sck, and ws). the forward control channel (fcc) bit carries the forward control data. the last bit (pcb) is the parity bit of the previous 23 or 31 bits. reverse control channel the MAX9259/max9260 use the reverse control channel to send i 2 c/uart and interrupt signals in the opposite direction of the video stream from the deserializer to the serializer. the reverse control channel and forward video data coexist on the same twisted pair forming a bidirectional link. the reverse control channel operates independently from the forward control channel. the reverse control channel is available 500 f s after power- up. the MAX9259 temporarily disables the reverse con - trol channel for 350 f s after starting/stopping the forward serial link. table 3. bus-width selection using bws figure 22. 24-bit mode serial link data format figure 23. 32-bit mode serial link data format 24 bits din0 din1 18-bit rgb data hsync, vsync, de audio channel bit forward control- channel bit packet parity check bit note: locations of the rgb data and control signals are interchangeable accordingly on both sides of the link. din17 din18 din19 din20 acb fcc pcb 24-bit rgb data hsync, vsync, de additional video data/ control bits audio channel bit forward control- channel bit packet parity check bit note: locations of the rgb data and control signals are interchangeable accordingly on both sides of the link. 32 bits din0 din1 din23 din24 din25 din26 din27 din28 acb fcc pcb bws input state bus width parallel bus signals used low 24 din[0:20]/dout[0:20], ws, sck, sd high 32 din[0:28]/dout[0:28], ws, sck, sd www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 28 _____________________________________________________________________________________ parallel data-rate selection the MAX9259/max9260 use the drs inputs to set the parallel data rate. set drs high to use a low-speed par - allel data rate in the range of 6.25mhz to 12.5mhz (32-bit mode) or 8.33mhz to 16.66mhz (24-bit mode). set drs low for normal operation with parallel data rates higher than 12.5mhz (32-bit mode) or 16.66mhz (24-bit mode). audio channel the i 2 s audio channel supports audio sampling rates from 8khz to 192khz and audio word lengths from 4 bits to 32 bits. the audio bit clock (sck) does not need to be synchronized with pclkin. the MAX9259 automatically encodes audio data into a single bit stream synchronous with pclkin. the max9260 decodes the audio stream and stores audio words in a fifo. audio rate detection uses an internal oscillator to continuously determine the audio data rate and output the audio in i 2 s format. the audio channel is enabled by default. when the audio channel is disabled, the sd pins on both sides are treated as a regular parallel data pin. pclk_ frequencies can limit the maximum supported audio sampling rate. table 4 lists the maximum audio sampling rate for various pclk_ frequencies. spread- spectrum settings do not affect the i 2 s data rate or ws clock frequency. additional mclk output for audio applications some audio dacs such as the max9850 do not require a synchronous main clock (mclk), while other dacs require mclk to be a specific multiple of ws. if an audio dac chip needs the mclk to be a multiple of ws, syn - chronize the i 2 s audio data with pclk_ of the gmsl, which is typical for most applications. select the pclk_ to be the multiple of ws, or use a clock synthesis chip, such as the max9491, to regenerate the required mclk from pclk_ or sck. for audio applications that cannot directly use the pclkout output, the max9260 provides a divided mclk output on dout28 at the expense of one less parallel line in 32-bit mode (24-bit mode is not affected). by default, dout28 operates as a parallel data output and mclk is turned off. set mclkdiv (max9260 regis - ter 0x12, d[6:0]) to a non-zero value to enable the mclk output. set mclkdiv to 0x00 to disable mclk and set dout28 as a parallel data output. the output mclk frequency is: src mclk f f mclkdiv = where f src is the mclk source frequency (table 5) and mclkdiv is the divider ratio from 1 to 127. table 4. maximum audio sampling rates for various pclk_ frequencies word length (bits) pclk_ frequency (drs = low) (mhz) pclk_ frequency (drs = high) (mhz) 12.5 15 16.6 > 20 6.25 7.5 8.33 > 10 8 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192 16 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192 18 185.5 > 192 > 192 > 192 185.5 > 192 > 192 > 192 20 174.6 > 192 > 192 > 192 174.6 > 192 > 192 > 192 24 152.2 182.7 > 192 > 192 152.2 182.7 > 192 > 192 32 123.7 148.4 164.3 > 192 123.7 148.4 164.3 > 192 www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 ______________________________________________________________________________________ 29 choose mclkdiv values so that f mclk is not greater than 60mhz. mclk frequencies derived from pclk_ (mclksrc = 0) are not affected by spread-spectrum settings in the deserializer (max9260). enabling spread spectrum in the serializer (MAX9259), however, intro - duces spread spectrum into mclk. spread-spectrum settings of either device do not affect mclk frequencies derived from the internal oscillator. the internal oscilla - tor frequency ranges from 100mhz to 150mhz over all process corners and operating conditions. control-channel and register programming the f c uses the control link to send and receive control data over the stp link simultaneously with the high-speed data. configuring the cds pin allows the f c to control the link from either the MAX9259 or the max9260 side to sup - port video-display or image-sensing applications. the control link between the f c and the MAX9259 or max9260 runs in base mode or bypass mode accord - ing to the mode selection (ms) input of the device con - nected to the f c. base mode is a half-duplex control link and the bypass mode is a full-duplex control link. in base mode, the f c is the host and accesses the registers of both the MAX9259 and max9260 from either side of the link by using the gmsl uart protocol. the f c can also program the peripherals on the remote side by sending the uart packets to the MAX9259 or max9260, with uart packets converted to i 2 c by the device on the remote side of the link (max9260 for lcd or MAX9259 for image-sensing applications). the f c communicates with a uart peripheral in base mode (through inttype register settings) using the half-duplex default gmsl uart protocol of the MAX9259 and max9260. the device addresses of the MAX9259 and max9260 in the base mode are programmable. the default values are 0x80 and 0x90, respectively. in base mode, when the peripheral interface uses i 2 c (default), the MAX9259/max9260 only convert packets that have device addresses different from those of the MAX9259 or max9260 to i 2 c. the converted i 2 c bit rate is the same as the original uart bit rate. in bypass mode, the f c bypasses the MAX9259/ max9260 and communicates with the peripherals direct - ly using its own defined uart protocol. the f c cannot access the MAX9259/max9260s registers in this mode. peripherals accessed through the forward control chan - nel using the uart interface need to handle at least one pclk_ period of jitter due to the asynchronous sampling of the uart signal by pclk_. the MAX9259 embeds control signals going to the max9260 in the high-speed forward link. do not send a low value longer than 100 f s in either base or bypass mode. the max9260 uses a proprietary differential line coding to send signals back towards the MAX9259. the speed of the control link ranges from 100kbps to 1mbps in both directions. the MAX9259/max9260 automatically detect the control-channel bit rate in base mode. packet bit rates can vary up to 3.5x from the previous bit rate (see the changing the data frequency section). figure 24 shows the uart protocol for writing and reading in base mode between the f c and the MAX9259/max9260. figure 25 shows the uart data format. even parity is used. figures 26 and 27 detail the formats of the sync byte (0x79) and ack byte (0xc3). the f c and the con - nected slave chip generate the sync byte and ack byte, respectively. certain events such as device wake- up and interrupt generate signals on the control path and should be ignored by the f c. all data written to the inter - nal registers do not take affect until after the acknowl - edge byte is sent. this allows the f c to verify that write commands are processed without error, even if the result of the write command directly affects the serial link. the slave uses the sync byte to synchronize with the host uart data rate automatically. if the int or ms inputs of the max9260 toggles while there is control-channel com - munication, the control-channel communication can be corrupted. in the event of a missed acknowledge, the f c table 5. max9260 f src settings mclksrc setting (register 0x12, d7) data-rate setting bit-width setting mclk source frequency (f src ) 0 high speed 24-bit mode 3 x f pclkout 32-bit mode 4 x f pclkout low speed 24-bit mode 6 x f pclkout 32-bit mode 8 x f pclkout 1 internal oscillator (120mhz typ) www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 30 _____________________________________________________________________________________ figure 24. uart protocol for base mode figure 25. uart data format for base mode figure 26. sync byte (0x79) figure 27. ack byte (0xc3) should assume there was an error in the packet when the slave device receives it, or that an error occurred during the response from the slave device. in base mode, the f c must keep the uart tx/rx lines high for 16 bit times before starting to send a new packet. as shown in figure 28, the remote-side device converts the packets going to or coming from the peripherals from the uart format to the i 2 c format and vice versa. the remote device removes the byte number count and adds or receives the ack between the data bytes of i 2 c. the i 2 cs data rate is the same as the uart data rate. interfacing command-byte-only i 2 c devices the MAX9259/max9260 uart-to-i 2 c conversion inter - faces with devices that do not require register address - es, such as the max7324 gpio expander. change the communication method of the i 2 c master using the i2cmethod bit. i2cmethod = 1 sets command-byte- only mode, while i2cmethod = 0 sets normal mode where the first byte in the data stream is the register address. in this mode, the i 2 c master ignores the reg - ister address byte and directly reads/writes the subse - quent data bytes (figure 29). write data format sync dev addr + r/w reg addr number of bytes sync dev addr + r/w reg addr number of bytes byte 1 byte n ack byte n byte 1 ack master reads from slave read data frmat master writes to slave master writes to slave master reads from slave start d0 d1 d2 d3 d4 d5 d6 d7 parity stop 1 uart frame frame 1 frame 2 frame 3 stop start stop start start d0 1 0 0 1 1 1 1 0 d1 d2 d3 d4 d5 d6 d7 parity stop start d0 1 1 0 0 0 0 1 1 d1 d2 d3 d4 d5 d6 d7 parity stop www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 ______________________________________________________________________________________ 31 figure 28. format conversion between uart and i 2 c with register address (i2cmethod = 0) figure 29. format conversion between uart and i 2 c in command-byte-only mode (i2cmethod = 1) 11 sync frame register address number of bytes device id + wr data 0 dev id a 11 11 11 11 data n 11 11 s 1 1 1 ack frame 7 : master to slave 8 MAX9259/max9260 peripheral w 1 reg addr 8 a 1 1 8 1 11 sync frame register address number of bytes device id + rd 11 11 11 11 ack frame data 0 11 data n 11 uart-to-i 2 c conversion of write packet (i2cmethod = 0) uart-to-i 2 c conversion of read packet (i2cmethod = 0) s: start p: stop a: acknowledge : slave to master data 0 a data n a p dev id a s 1 1 7 w 1 dev id a s 1 1 7 r 1 data n p 1 8 a 1 data 0 8 a 1 reg addr 8 a 1 fc MAX9259/max9260 fc MAX9259/max9260 MAX9259/max9260 peripheral : master to slave MAX9259/max9260 MAX9259/max9260 MAX9259/max9260 uart-to-i 2 c conversion of read packet (i2cmethod = 1) uart-to-i 2 c conversion of write packet (i2cmethod = 1) fc MAX9259/max9260 fc sync frame 11 11 11 11 11 11 11 11 11 11 11 11 11 11 device id + rd register address number of bytes sync frame device id + wr register address number of bytes data 0 data n ack frame ack frame data 0 data n data n a data 0 w a dev id s a p peripheral peripheral s 1 1 1 8 8 8 1 1 1 1 7 1 1 8 1 1 1 7 dev id r a a a p data 0 data n : slave to master s: start p: stop a: acknowledge www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 32 _____________________________________________________________________________________ interrupt control the int of the MAX9259 is the interrupt output and the int of the max9260 is the interrupt input. the interrupt output on the MAX9259 follows the transitions at the interrupt input of the max9260. this interrupt function supports remote-side functions such as touch-screen peripherals, remote power-up, or remote monitoring. interrupts that occur during periods where the reverse control channel is disabled, such as link startup/shut - down, are automatically resent once the reverse control channel becomes available again. bit d4 of register 0x06 in the max9260 also stores the interrupt input state. writing to the setint register bit also sets the int output of the MAX9259. in addition, the f c sets the int output of the MAX9259 by writing to the setint register bit. in normal operation, the state of the interrupt output chang - es when the interrupt input on the max9260 toggles. preemphasis driver the serial line driver in the MAX9259 employs current- mode logic (cml) signaling. the driver generates an adjustable preemphasized waveform according to the cable length and characteristics. there are 13 preemphasis settings, as shown in table 6. negative preemphasis levels are deemphasis levels in which the preemphasized swing level is the same as normal swing, but the no-transition data is deemphasized. program the preemphasis levels through register 0x05 d[3:0] of the MAX9259. this preemphasis function compensates the high-frequency loss of the cable and enables reliable transmission over longer link distances. additionally, a lower power drive mode can be entered by program - ming cmllvl bits (0x05 d[5:4]) to reduce the driver strength down to 75% (cmllvl = 10), or 50% (cmllvl = 01) from 100% (cmllvl = 11, default). line equalizer the max9260 includes an adjustable line equalizer to further compensate cable attenuation at high frequen - cies. the cable equalizer has 11 selectable levels of compensation from 2.1db to 13db (table 7). the eqs input selects the default equalization level at power-up. the state of eqs is latched upon power-up or when resuming from power-down mode. to select other equalization levels, set the corresponding register bits in the max9260 (0x05 d[3:0]). use equalization in the max9260, together with preemphasis in the MAX9259 to create the most reliable link for a given cable. table 6. MAX9259 cml driver strength (default level, cmllvl = 11) * negative preemphasis levels denote deemphasis. preemphasis level (db)* preemphasis setting (0x05, d[3:0]) i cml (ma) i pre (ma) single-ended voltage swing max (mv) min (mv) -6.0 0100 12 4 400 200 -4.1 0011 13 3 400 250 -2.5 0010 14 2 400 300 -1.2 0001 15 1 400 350 0 0000 16 0 400 400 1.1 1000 16 1 425 375 2.2 1001 16 2 450 350 3.3 1010 16 3 475 325 4.4 1011 16 4 500 300 6.0 1100 15 5 500 250 8.0 1101 14 6 500 200 10.5 1110 13 7 500 150 14.0 1111 12 8 500 100 www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 ______________________________________________________________________________________ 33 spread spectrum to reduce the emi generated by the transitions on the serial link and parallel outputs, both the MAX9259 and max9260 support spread spectrum. turning on spread spectrum on the max9260 spreads the parallel video outputs. turning on spread spectrum on the MAX9259 spreads the serial link, along with the max9260 parallel outputs. do not enable spread spectrum for both the MAX9259 and max9260. the six selectable spread- spectrum rates at the MAX9259 serial output are q 0.5%, q 1%, q 1.5%, q 2%, q 3%, and q 4% (table 8). some spread-spectrum rates can only be used at lower pclk_ frequencies (table 9). there is no pclk_ frequency limit for the 0.5% spread rate. the two selectable spread- spectrum rates at the max9260 parallel outputs are q 2% and q 4% (table 10). set the MAX9259 ssen input high to select 0.5% spread at power-up and ssen input low to select no spread at power-up. set the max9260 ssen input high to select 2% spread at power-up and ssen input low to select no spread at power-up. the state of ssen is latched upon power-up or when resuming from power-down mode. whenever the MAX9259 spread spectrum is turned on table 7. max9260 cable equalizer boost levels table 8. MAX9259 serial output spread table 9. MAX9259 spread-spectrum rate limitations boost setting (0x05 d[3:0]) typical boost gain (db) 0000 2.1 0001 2.8 0010 3.4 0011 4.2 0100 5.2 power-up default (eqs = high) 0101 6.2 0110 7 0111 8.2 1000 9.4 1001 10.7 power-up default (eqs = low) 1010 11.7 1011 13 ss spread (%) 000 no spread spectrum. power-up default when ssen = low. 001 q 0.5% spread spectrum. power-up default when ssen = high. 010 q 1.5% spread spectrum 011 q 2% spread spectrum 100 no spread spectrum 101 q 1% spread spectrum 110 q 3% spread spectrum 111 q 4% spread spectrum 24-bit mode pclkin frequency (mhz) 32-bit mode pclkin frequency (mhz) serial link bit rate (mbps) available spread rates < 33.3 < 25 < 1000 all rates available 33.3 to < 66.7 20 to < 50 1000 to < 2000 1.5%, 1.0%, 0.5% 66.7+ 50+ 2000+ 0.5% www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 34 _____________________________________________________________________________________ or off, the serial link automatically restarts and remains unavailable while the max9260 relocks to the serial data. turning on spread spectrum on either the MAX9259 or max9260 side does not affect the audio data stream. changes in the MAX9259 spread settings only affect mclk output if it is derived from pclk_ (mclksrc = 0). both devices include a sawtooth divider to control the spread-modulation rate. autodetection or manual pro - gramming of the pclk_ operation range guarantees a spread-spectrum modulation frequency within 20khz to 40khz. additionally, manual configuration of the saw - tooth divider (sdiv, 0x03 d[5:0]) allows the user to set a specific modulation frequency for a specific pclk_ rate. always keep the modulation frequency between 20khz to 40khz to ensure proper operation. manual programming of the spread- spectrum divider the modulation rates for the MAX9259 or the max9260 relate to the pclk_ frequency as follows: ( ) pclk_ m f f 1 drs mod sdiv = + where: f m = modulation frequency drs = drs pin input value (0 or 1) f pclk_ = parallel clock frequency (12.5mhz to 104mhz) mod = modulation coefficient given in table 11 for the MAX9259 and table 12 for the max9260 sdiv = 6-bit (MAX9259) or 5-bit (max9260) sdiv setting, manually programmed by the f c table 10. max9260 parallel output spread table 11. MAX9259 modulation coefficients and maximum sdiv settings table 12. max9260 modulation coefficients and maximum sdiv settings ss spread (%) 00 no spread spectrum. power-up default when ssen = low. 01 q 2% spread spectrum. power-up default when ssen = high. 10 no spread spectrum 11 q 4% spread spectrum bit-width mode spread-spectrum setting (%) modulation coefficient (decimal) sdiv upper limit (deci - mal) 32-bit 1 104 40 0.5 104 63 3 152 27 1.5 152 54 4 204 15 2 204 30 24-bit 1 80 52 0.5 80 63 3 112 37 1.5 112 63 4 152 21 2 152 42 spread-spectrum setting (%) modulation coefficient (deci - mal) sdiv upper limit (decimal) 4 208 15 2 208 30 www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 ______________________________________________________________________________________ 35 to program the sdiv setting, first look up the modulation coefficient according to the part number and desired bit-width and spread-spectrum settings. solve the above equation for sdiv using the desired parallel clock and modulation frequencies. if the calculated sdiv value is larger than the maximum allowed sdiv value in tables 11 or 12, set sdiv to the maximum value. sleep mode the serializer/deserializer include a low-power sleep mode to reduce power consumption on the device not attached to the f c (max9260 in lcd applications and MAX9259 in camera applications). set the correspond - ing remote ics sleep bit to 1 to initiate sleep mode. the MAX9259 sleeps immediately after setting its sleep = 1. the max9260 sleeps after serial link inactivity or 8ms (whichever arrives first) after setting its sleep = 1. see the link startup procedure section for details on waking up the device for different f c and starting conditions. the f c side device cannot enter into sleep mode, and its sleep bit remains at 0. use the pwdn input pin to bring the f c side device into a low-power state. configuration link mode the MAX9259/max9260 include a low-speed configura - tion link to allow control-data connection between the two devices in the absence of a valid parallel clock input. in either display or camera applications, the configuration link can be used to program equalizer/preemphasis or other registers before establishing the video link. an internal oscillator provides pclk_ for establishing the serial configuration link between the MAX9259 and max9260. the parallel output clock and data lines are disabled in the max9260. the lock output remains low even after a successful configuration link lock. set clinken = 1 on the MAX9259 to turn on the configura - tion link. the configuration link remains active as long as the video link has not been enabled. the video link over - rides the configuration link and attempts to lock when seren = 1. link startup procedure table 13 lists four startup cases for video-display applications. table 14 lists two startup cases for image- sensing applications. in either display or image-sensing applications, the control link is always available after the high-speed data link or the configuration link is established and the MAX9259/max9260 registers or the peripherals are ready for programming. video-display applications for the video-display application, with a remote display unit, connect the f c to the serializer (MAX9259) and set cds = low for both the MAX9259 and max9260. table 13 summarizes the four startup cases based on the set - tings of autos and ms. case 1: autostart mode after power-up or when pwdn transitions from low to high for both the serializer and deserializer, the serial link establishes if a stable pclk_ is present. the MAX9259 locks to pclk_ and sends the serial data to the max9260. the max9260 then detects activity on the serial link and locks to the input serial data. case 2: standby start mode after power-up, or when pwdn transitions from low to high for both the serializer and deserializer, the max9260 starts up in sleep mode, and the MAX9259 stays in standby mode (does not send serial data). use the f c and program the MAX9259 to set seren = 1 to establish a video link or clinken = 1 to establish the configuration link. after locking to a stable pclk_ (for seren = 1) or the internal oscillator (for clinken = 1), the MAX9259 sends a wake-up signal to the deserial - izer. the max9260 exits sleep mode after locking to the serial data and sets sleep = 0. if after 8ms the deserial - izer does not lock to the input serial data, the max9260 goes back to sleep, and the internal sleep bit remains uncleared (sleep = 1). case 3: remote side autostart mode after power-up, or when pwdn transitions from low to high, the remote device (max9260) starts up and tries to lock to an incoming serial signal with sufficient power. the host side (MAX9259) is in standby mode and does not try to establish a link. use the f c and program the MAX9259 to set seren = 1 (and apply a stable pclk_) to establish a video link, or clinken = 1 to establish the configuration link. in this case, the max9260 ignores the short wake-up signal sent from the MAX9259. case 4: remote side in sleep mode after power-up or when pwdn transitions from low to high, the remote device (max9260) starts up in sleep mode. the high-speed link establishes automatically after MAX9259 powers up with a stable pclk_ and sends a wake-up signal to the max9260. use this mode in applications where the max9260 powers up before the MAX9259. www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 36 _____________________________________________________________________________________ table 13. startup selection for video-display applications (cds = low) figure 30. MAX9259 state diagram, cds = low (lcd application) power-down or power-off power-on idle config link operating all states video link locking video link unlocked autos pin setting low high 1 0 seren bit power-up value pwdn = low or power-off seren = 1, pclkin running seren = 0, or no pclkin seren = 0, no pclkin pwdn = high power-on, autos = low config link starting program registers video link operating prbsen = 0 prbsen = 1 video link prbs test clinken = 0 or seren = 1 clinken = 1 clinken = 0 or seren = 1 config link unlocked video link locked locked config link pwdn = high, power-on autos = low case autos (MAX9259) MAX9259 power-up state ms (max9260) max9260 power-up state link startup mode 1 low serialization enabled low normal (sleep = 0) both devices power up with serial link active (autostart) 2 high serialization dis - abled high sleep mode (sleep = 1) serial link is disabled and the max9260 powers up in sleep mode. set seren = 1 or clinken = 1 in the MAX9259 to start the serial link and wake up the max9260. 3 high serialization dis - abled low normal (sleep = 0) both devices power up in nor - mal mode with the serial link is disabled. set seren = 1 or clinken = 1 in the MAX9259 to start the serial link. 4 low serialization enabled high sleep mode (sleep = 1) max9260 starts in sleep mode. link autostarts upon MAX9259 power-up. use this case when the max9260 powers up before the MAX9259. www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 ______________________________________________________________________________________ 37 image-sensing applications for image-sensing applications, with remote camera unit(s), connect the f c to the deserializer (max9260) and set cds = high for both the MAX9259 and max9260. the max9260 powers up normally (sleep = 0) and con - tinuously tries to lock to a valid serial input. table 14 summarizes the two startup cases, based on the state of the MAX9259 autos pin. case 1: autostart mode after power-up, or when pwdn transitions from low to high, the MAX9259 locks to a stable pclkin and sends the high-speed data to the max9260. the max9260 locks to the serial data and outputs the parallel video data and pclkout. case 2: sleep mode after power-up, or when pwdn transitions from low to high, the MAX9259 starts up in sleep mode. to wake up the MAX9259, use the f c to send a regular uart frame containing at least three rising edges (e.g., 0x66), at a bit rate no greater than 1mbps. the low-power wake-up receiver of the MAX9259 detects the wake-up frame over the reverse control channel and powers up. reset the sleep bit (sleep = 0) of the MAX9259 using a regular control-channel write packet to power up the device fully. send the sleep bit write packet at least 500 f s after the wake-up frame. the MAX9259 goes back to sleep mode if its sleep bit is not cleared within 8ms (typ) after detect - ing a wake-up frame. figure 31. max9260 state diagram, cds = low (lcd application) table 14. startup selection for image-sensing applications (cds = high) sleep ms pin setting low high 0 1 sleep bit power-up value config link operating program registers power-off high to low sleep = 1, video link or config link not locked after 8ms power-on idle wake-up signal serial port locking signal detected config link unlocked config link locked video link locked video link unlocked 0 sleep 0 sleep all states int changes from low to high or pwdn = low or send int to MAX9259 pwdn = high, power-on power-down or power-off serial link activity stops or 8ms elapses after fc sets sleep = 1 video link operating prbsen = 0 prbsen = 1 video link prbs test case autos (MAX9259) MAX9259 power-up state max9260 power-up state link startup mode 1 low serialization enabled normal (sleep = 0) autostart 2 high sleep mode (sleep = 1) normal (sleep = 0) MAX9259 is in sleep mode. wake up the MAX9259 through the control channel ( f c attached to max9260). www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 38 _____________________________________________________________________________________ figure 32. MAX9259 state diagram, cds = high (camera application) figure 33. max9260 state diagram, cds = high (camera application) low high 1 0 0 seren sleep 1 power-up value seren = 0 for > 8ms video link operating video link prbs test wake-up sleep = 1 wake-up signal reverse link config link started clinken = 0 or seren = 1 clinken = 1 unlocked locked config link config link sleep = 0, sleep power-on idle power-off all states pwdn = low or sleep = 1 power-down or power-off autos = low pwdn = high, power-on video link locking autos pin setting config link operating program registers clinken = 0 or seren = 1 video link locked video link unlocked prbsen = 0 prbsen = 1 seren = 1, pclkin running seren = 0 or no pclkin seren = 0 or no pclkin pwdn = high, power-on, autos = high sleep = 0, sleep = 1 power-on idle serial port locking all states power-down or power-off no signal detected pwdn = high, power on config link operating video link operating video link locked video link unlocked prbsen = 0 prbsen = 1 video link prbs test config link unlocked config link locked signal detected program registers pwdn = low or power-off (reverse channel active) www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 ______________________________________________________________________________________ 39 applications information max9260 error checking the max9260 checks the serial link for errors and stores the number of detected decoding errors in the 8-bit register (decerr, 0x0d). if a large number of decoding errors are detected within a short duration, the deserial - izer loses lock and stops the error counter. the deserial - izer then attempts to relock to the serial data. decerr resets upon successful video link lock, successful readout of decerr (through uart), or whenever auto- error reset is enabled. the max9260 does not check for decoding errors during the internal prbs test and decerr is reset to 0x00. err output the max9260 has an open-drain err output. this output asserts low whenever the number of decoding errors exceed the error threshold (errthr, 0x0c) dur - ing normal operation, or when at least one prbs error is detected during prbs test. err reasserts high when - ever decerr (0x0d) resets, due to decerr readout, video link lock, or autoerror reset. autoerror reset the default method to reset errors is to read the respec - tive error registers in the max9260 (0x0d, 0x0e). auto- error reset clears the decoding-error counter (decerr) and the err output ~1 f s after err goes low. autoerror reset is disabled on power-up. enable autoerror reset through autorst (0x06 d6). autoerror reset does not run when the device is in prbs test mode. self prbs test the MAX9259/max9260 link includes a prbs pat - tern generator and bit-error verification function. set prbsen = 1 (0x04 d5) first in the MAX9259 and then the max9260 to start the prbs test. set prbsen = 0 (0x04 d5) first in the max9260 and then the MAX9259 to exit the prbs self test. the max9260 uses an 8-bit register (0x0e) to count the number of detected errors. the control link also controls the start and stop of the error counting. during prbs mode, the device does not count decoding errors and the err output reflects prbs errors only. autoerror reset does not run when the device is in prbs mode. microcontrollers on both sides of the gmsl link (dual c control) usually the f c is either on the serializer (MAX9259) side for video-display applications, or on the deserial - izer (max9260) side for image-sensing applications. for the former case, both the cds pins of the MAX9259/ max9260 are set to low, and for the later case, the cds pins are set to high. however, if the cds pin of the MAX9259 is low and the cds pin of the max9260 is high, then the MAX9259/max9260 can both connect to f cs simultaneously. in such a case, the f cs on either side can communicate with the MAX9259/max9260 uart protocol. contentions of the control link may happen if the f cs on both sides are using the link at the same time. the MAX9259/max9260 do not provide the solution for contention avoidance. the serializer/deserealizer do not send an acknowledge frame when communication fails due to contention. users can always implement a higher- layer protocol to avoid the contention. in addition, if uart communication across the serial link is not required, the f cs can disable the forward and reverse control channel through the fwdccen and revccen bits (0x04 d[1:0]) in the MAX9259/max9260. uart communication across the serial link is stopped and contention between f cs no longer occurs. during the dual f c operation, if one of the cds pins on either side changes state, the link resumes the corresponding state described in the link startup procedure section. as an example of dual f c use in an image-sensing link, the MAX9259 may be in sleep mode and waiting to be waked up by the max9260. after wake-up, the serializer- side f c sets the MAX9259 cds pin low and assumes master control of the MAX9259 registers. jitter-filtering pll in some applications, the parallel bus input clock to the MAX9259 (pclkin) includes noise, which reduces link reliability. the MAX9259 has a narrow-band jitter-filtering pll to attenuate frequency components outside the plls bandwidth (< 100khz typ). enable the jitter-filtering pll by setting disfpll = 0 (0x05 d6). changing the data frequency both the video data rate (f pclk_ ) and the control data rate (f uart ) can be changed on-the-fly to support applications with multiple clock speeds. slow speed/ performance modes allow significant power savings when a systems full capabilities are not required. enable the MAX9259/max9260 link after pclk_ stabilizes. stop pclkin for 5s and restart the serial link or toggle seren after each change in the parallel clock frequency to recalibrate any automatic settings if a clean frequency change cannot be guaranteed. the reverse control channel remains unavailable for 350 f s after serial link start or stop. limit on-the-fly changes in f uart to fac - tors of less than 3.5 at a time to ensure that the device www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 40 _____________________________________________________________________________________ recognizes the uart sync pattern. for example, when lowering the uart frequency from 1mbps to 100kbps, first send data at 333kbps and then at 100kbps to have reduction ratios of 3 and 3.333, respectively. lock output loopback connect the lock output to the int input of the max9260 to loopback lock to the MAX9259. the interrupt output on the MAX9259 follows the transitions at the lock output of the max9260. reverse-channel communication does not require an active forward link to operate and accurately tracks the lock status of the video link. lock asserts for video link only and not for the configuration link. max9260 gpios the max9260 has two open-drain gpios available. gpio1out and gpio0out (0x06 d3, d1) set the output state of the gpios. the gpio input buffers are always enabled. the input states are stored in gpio1 and gpio0 (0x06 d2, d0). set gpio1out/gpio0out to 1 when using gpio1/gpio0 as an input. line-fault detection the line-fault detector in the MAX9259 monitors for line failures such as short to ground, short to power supply, and open link for system fault diagnosis. figure 3 shows the required external resistor connections. lflt = low when a line fault is detected and lflt = high when the line returns to normal. the line-fault type is stored in 0x08 d[3:0] of the MAX9259. the fault-detector thresh - old voltages are referenced to the MAX9259 ground. additional passive components set the dc level of the cable (figure 3). if the MAX9259 and max9260 grounds are different, the link dc voltage during normal operation can vary and cross one of the fault-detection thresholds. for the fault-detection circuit, select the resistors power rating to handle a short to the battery. table 15 lists the mapping for line-fault types. staggered parallel data outputs the max9260 staggers the parallel data outputs to reduce emi and noise. staggering outputs also reduce the power-supply transient requirements. by default, the deserializer staggers outputs according to table 16. disable output staggering through the disstag bit (0x06 d7) choosing i 2 c/uart pullup resistors both i 2 c/uart open-drain lines require pullup resistors to provide a logic-high level. there are tradeoffs between power dissipation and speed, and a compromise must be made in choosing pullup resistor values. every device connected to the bus introduces some capacitance even when the device is not in operation. i 2 c specifies 300ns rise times to go from low to high (30% to 70%) for fast mode, which is defined for data rates up to 400kbps (see the i 2 c specifications in the electrical characteristics table for details). to meet the fast-mode rise-time requirement, choose the pullup resistors so that rise time t r = 0.85 x r pullup x c bus < 300ns. the waveforms are not recognized if the transition time becomes too table 15. MAX9259 line-fault mapping table 16. staggered output delay register address bits name value line-fault type 0x08 d[3:2] lfneg 00 negative cable wire shorted to battery 01 negative cable wire shorted to ground 10 normal operation 11 negative cable wire open d[1:0] lfpos 00 positive cable wire shorted to battery 01 positive cable wire shorted to ground 10 normal operation 11 positive cable wire open output output delay relative to dout0 (ns) disstag = 0 disstag = 1 dout0Cdout5, dout21, dout22 0 0 dout6Cdout10, dout23, dout24 0.5 0 dout11Cdout15, dout25, dout26 1 0 dout16Cdout20, dout27, dout28 1.5 0 pclkout 0.75 0 www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 ______________________________________________________________________________________ 41 slow. the MAX9259/max9260 support i 2 c/uart rates up to 1mbps. ac-coupling ac-coupling isolates the receiver from dc voltages up to the voltage rating of the capacitor. four capacitorstwo at the serializer output and two at the deserializer input are needed for proper link operation and to provide protection if either end of the cable is shorted to a high voltage. ac-coupling blocks low-frequency ground shifts and low-frequency common-mode noise. selection of ac-coupling capacitors voltage droop and the digital sum variation (dsv) of transmitted symbols cause signal transitions to start from different voltage levels. because the transition time is finite, starting the signal transition from different volt - age levels causes timing jitter. the time constant for an ac-coupled link needs to be chosen to reduce droop and jitter to an acceptable level. the rc network for an ac-coupled link consists of the cml receiver termination resistor (r tr ), the cml driver termination resistor (r td ), and the series ac-coupling capacitors (c). the rc time constant for four equal-value series capacitors is (c x (r td + r tr ))/4. r td and r tr are required to match the transmission line impedance (usually 100 i ). this leaves the capacitor selection to change the system time con - stant. use at least 0.2 f f (100v) high-frequency surface- mount ceramic capacitors to pass the lower speed reverse-channel signal. use capacitors with a case size less than 3.2mm x 1.6mm to have lower parasitic effects to the high-speed signal. power-supply circuits and bypassing the MAX9259 uses an avdd and dvdd of 1.7v to 1.9v. the max9260 uses an avdd and dvdd of 3.0v to 3.6v. all single-ended inputs and outputs on the MAX9259/ max9260 derive power from an iovdd of 1.7v to 3.6v. the input levels or output levels scale with iovdd. proper voltage-supply bypassing is essential for high- frequency circuit stability. cables and connectors interconnect for cml typically has a differential imped - ance of 100 i . use cables and connectors that have matched differential impedance to minimize impedance discontinuities. twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less emi due to magnetic- field canceling effects. balanced cables pick up noise as common mode rejected by the cml receiver. table 17 lists the suggested cables and connectors used in the gmsl link. board layout separate the parallel signals and cml high-speed serial signals to prevent crosstalk. use a four-layer pcb with separate layers for power, ground, cml, and digital signals. layout pcb traces close to each other and have a 100 i differential characteristic impedance. the trace dimensions depend on the type of trace used (microstrip or stripline). note that two 50 i pcb traces do not have 100 i differential impedance when brought close togetherthe impedance goes down when the traces are brought closer. route the pcb traces for a cml channel (there are two conductors per cml channel) in parallel to maintain the differential characteristic impedance. avoid vias. if vias must be used, use only one pair per cml channel and place the via for each line at the same point along the length of the pcb traces. this way, any reflections occur at the same time. do not make vias into test points for table 17. suggested connectors and cables for gmsl supplier connector cable jae electronics, inc. mx38-ff a-bw-lxxxxx nissei electric co., ltd. gt11l-2s f-2wme awg28 rosenberger hochfrequenztechnik gmbh d4s10a-40ml5-z dacar 538 www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 42 _____________________________________________________________________________________ ate. keep pcb traces that make up a differential pair equal in length to avoid skew within the differential pair. esd protection the MAX9259/max9260 esd tolerance is rated for human body model, iec 61000-4-2, and iso 10605. the iso 10605 and iec 61000-4-2 standards specify esd tolerance for electronic systems. serial outputs on the MAX9259 and serial inputs on the max9260 meet iso 10605 esd protection and iec 61000-4-2 esd protec - tion. all other pins meet the human body model esd tolerances. the human body model discharge compo - nents are c s = 100pf and r d = 1.5k i (figure 34). the iec 61000-4-2 discharge components are c s = 150pf and r d = 330 i (figure 35). the iso 10605 discharge components are c s = 330pf and r d = 2k i (figure 36). figure 34. human body model esd test circuit figure 35. iec 61000-4-2 contact discharge esd test circuit figure 36. iso 10605 contact discharge esd test circuit storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance 1mi r d 1.5ki c s 100pf c s 150pf storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 330i storage capacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 2ki c s 330pf www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 ______________________________________________________________________________________ 43 table 18. MAX9259 register table (see table 1 for default value details) register address bits name value function default value 0x00 d[7:1] serid xxxxxxx serializer device address 1000000 d0 0 reserved 0 0x01 d[7:1] desid xxxxxxx deserializer device address 1001000 d0 0 reserved 0 0x02 d[7:5] ss 000 no spread spectrum. power-up default when ssen = low . 000, 001 001 q 0.5% spread spectrum. power-up default when ssen = high . 010 q 1.5% spread spectrum 011 q 2% spread spectrum 100 no spread spectrum 101 q 1% spread spectrum 110 q 3% spread spectrum 111 q 4% spread spectrum d4 audioen 0 disable i 2 s channel 1 1 enable i 2 s channel d[3:2] prng 00 12.5mhz to 25mhz pixel clock 11 01 25mhz to 50mhz pixel clock 10 50mhz to 104mhz pixel clock 11 automatically detect the pixel clock range d[1:0] srng 00 0.5 to 1gbps serial-data rate 11 01 1 to 2gbps serial-data rate 10 2 to 3.125gbps serial-data rate 11 automatically detect serial-data rate 0x03 d[7:6] autofm 00 calibrate spread-modulation rate only once after locking 00 01 calibrate spread-modulation rate every 2ms after locking 10 calibrate spread-modulation rate every 16ms after locking 11 calibrate spread-modulation rate every 256ms after locking d[5:0] sdiv 000000 autocalibrate sawtooth divider 000000 xxxxxx manual sdiv setting (see the manual programming of the spread-spectrum divider section) www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 44 _____________________________________________________________________________________ table 18. MAX9259 register table (see table 1 for default value details) (continued) register address bits name value function default value 0x04 d7 seren 0 disable serial link. power-up default when autos = high . reverse-channel communication remains unavailable for 350 f s after the MAX9259 starts/stops the serial link. 0, 1 1 enable serial link. power-up default when autos = low . reverse-channel communication remains unavailable for 350 f s after the MAX9259 starts/stops the serial link. d6 clinken 0 disable configuration link 0 1 enable configuration link d5 prbsen 0 disable prbs test 0 1 enable prbs test d4 sleep 0 normal mode. default value depends on cds and autos pin values at power-up. 0, 1 1 activate sleep mode. default value depends on cds and autos pin values at power-up. d[3:2] inttype 00 base mode uses i 2 c peripheral interface 00 01 base mode uses uart peripheral interface 10, 11 base mode peripheral interface disabled d1 revccen 0 disable reverse control channel from deserializer (receiving) 1 1 enable reverse control channel from deserializer (receiving) d0 fwdccen 0 disable forward control channel to deserializer (sending) 1 1 enable forward control channel to deserializer (sending) www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 ______________________________________________________________________________________ 45 table 18. MAX9259 register table (see table 1 for default value details) (continued) register address bits name value function default value 0x05 d7 i2cmethod 0 i 2 c conversion sends the register address 0 1 disable sending of i 2 c register address (command-byte-only mode) d6 disfpll 0 filter pll active 1 1 filter pll disabled d[5:4] cmllvl 00 do not use 11 01 200mv cml signal level 10 300mv cml signal level 11 400mv cml signal level d[3:0] preemp 0000 preemphasis off 0000 0001 -1.2db preemphasis 0010 -2.5db preemphasis 0011 -4.1db preemphasis 0100 -6.0db preemphasis 0101 do not use 0110 do not use 0111 do not use 1000 1.1db preemphasis 1001 2.2db preemphasis 1010 3.3db preemphasis 1011 4.4db preemphasis 1100 6.0db preemphasis 1101 8.0db preemphasis 1110 10.5db preemphasis 1111 14.0db preemphasis 0x06 d[7:0] 01000000 reserved 01000000 0x07 d[7:0] 00100010 reserved 00100010 0x08 d[7:4] 0000 reserved 0000 (read only) d[3:2] lfneg 00 negative cable wire shorted to battery 10 (read only) 01 negative cable wire shorted to ground 10 normal operation 11 negative cable wire open d[1:0] lfpos 00 positive cable wire shorted to battery 10 (read only) 01 positive cable wire shorted to ground 10 normal operation 11 positive cable wire open www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 46 _____________________________________________________________________________________ table 18. MAX9259 register table (see table 1 for default value details) (continued) table 19. max9260 register table x = dont care. register address bits name value function default value 0x0d d7 setint 0 set int low when setint transitions from 1 to 0 0 1 set int high when setint transitions from 0 to 1 d[6:4] 000 reserved 000 d[3:0] 1111 reserved 1111 0x1e d[7:0] id 00000001 device identifier (MAX9259 = 0x01) 00000001 (read only) 0x1f d[7:4] 0000 reserved 0000 (read only) d[3:0] revision xxxx device revision (read only) register address bits name value function default value 0x00 d[7:1] serid xxxxxxx serializer device address 1000000 d0 0 reserved 0 0x01 d[7:1] desid xxxxxxx deserializer device address 1001000 d0 0 reserved 0 0x02 d[7:6] ss 00 no spread spectrum. power-up default when ssen = low . 00, 01 01 q 2% spread spectrum. power-up default when ssen = high . 10 no spread spectrum 11 q 4% spread spectrum d5 0 reserved 0 d4 audioen 0 disable i 2 s channel 1 1 enable i 2 s channel d[3:2] prng 00 12.5mhz to 25mhz pixel clock 11 01 25mhz to 50mhz pixel clock 10 50mhz to 104mhz pixel clock 11 automatically detect the pixel clock range d[1:0] srng 00 0.5 to 1gbps serial-data rate 11 01 1 to 2gbps serial-data rate 10 2 to 3.125gbps serial-data rate 11 automatically detect serial-data rate www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 ______________________________________________________________________________________ 47 table 19. max9260 register table (continued) register address bits name value function default value 0x03 d[7:6] autofm 00 calibrate spread-modulation rate only once after locking 00 01 calibrate spread-modulation rate every 2ms after locking 10 calibrate spread-modulation rate every 16ms after locking 11 calibrate spread-modulation rate every 256ms after locking d5 0 reserved 0 d[4:0] sdiv 00000 autocalibrate sawtooth divider 00000 xxxxx manual sdiv setting (see the manual programming of the spread-spectrum divider section) 0x04 d7 locked 0 lock output is low 0 (read only) 1 lock output is high d6 outenb 0 enable outputs. a transition on enable changes the state of outenb. 0, 1 1 disable outputs. a transition on enable changes the state of outenb. d5 prbsen 0 disable prbs test 0 1 enable prbs test d4 sleep 0 normal mode default value depends on cds and ms pin values at power-up) 0, 1 1 activate sleep mode default value depends on cds and ms pin values at power-up) d[3:2] inttype 00 base mode uses i 2 c peripheral interface 00 01 base mode uses uart peripheral interface 10, 11 base mode peripheral interface disabled d1 revccen 0 disable reverse control channel to serializer (sending) 1 1 enable reverse control channel to serializer (sending) d0 fwdccen 0 disable forward control channel from serializer (receiving) 1 1 enable forward control channel from serializer (receiving) www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 48 _____________________________________________________________________________________ table 19. max9260 register table (continued) register address bits name value function default value 0x05 d7 i2cmethod 0 i 2 c conversion sends the register address 0 1 disable sending of i 2 c register address (command-byte-only mode) d[6:5] hpftune 00 7.5mhz equalizer highpass cutoff frequency 01 01 3.75mhz cutoff frequency 10 2.5mhz cutoff frequency 11 1.87mhz cutoff frequency d4 pdhf 0 high-frequency boosting enabled 0 1 high-frequency boosting disabled d[3:0] eqtune 0000 2.1db equalizer boost gain 0100, 1001 0001 2.8db equalizer boost gain 0010 3.4db equalizer boost gain 0011 4.2db equalizer boost gain 0100 5.2db equalizer boost gain. power-up default when eqs = high . 0101 6.2db equalizer boost gain 0110 7db equalizer boost gain 0111 8.2db equalizer boost gain 1000 9.4db equalizer boost gain 1001 10.7db equalizer boost gain. power-up default when eqs = low . 1010 11.7db equalizer boost gain 1011 13db equalizer boost gain 11xx do not use 0x06 d7 disstag 0 enable staggered outputs 0 1 disable staggered outputs d6 autorst 0 do not automatically reset error registers and outputs 0 1 automatically reset error registers and outputs d5 disint 0 enable interrupt transmission to serializer 0 1 disable interrupt transmission to serializer d4 int 0 int input = low (read only) 0 (read only) 1 int input = high (read only) d3 gpio1out 0 output low to gpio1 1 1 output high to gpio1 d2 gpio1 0 gpio1 is low 1 (read only) 1 gpio1 is high d1 gpio0out 0 output low to gpio0 1 1 output high to gpio0 d0 gpio0 0 gpio0 is low 1 (read only) 1 gpio0 is high www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 ______________________________________________________________________________________ 49 table 19. max9260 register table (continued) x = dont care. typical application circuit register address bits name value function default value 0x07 d[7:0] 01010100 reserved 01010100 0x08 d[7:0] 00110000 reserved 00110000 0x09 d[7:0] 11001000 reserved 11001000 0x0a d[7:0] 00010010 reserved 00010010 0x0b d[7:0] 00100000 reserved 00100000 0x0c d[7:0] errthr xxxxxxxx error threshold for decoding errors. err = low when decerr > errthr. 00000000 0x0d d[7:0] decerr xxxxxxxx decoding error counter. this counter remains zero while the device is in prbs test mode. 00000000 (read only) 0x0e d[7:0] prbserr xxxxxxxx prbs error counter 00000000 (read only) 0x12 d7 mclksrc 0 mclk derived from pclkout (see table 5) 0 1 mclk derived from internal oscillator d[6:0] mclkdiv 0000000 mclk disabled 0000000 xxxxxxx mclk divider 0x1e d[7:0] id 00000010 device identifier (max9260 = 0x02) 00000010 (read only) 0x1f d[7:4] 0000 reserved 0000 (read only) d[3:0] revision xxxx device revision (read only) pclk rgb hsync video ecu uart vsync tx rx int ims audio ws sck sd pclkin din(0:27) din28 cds autos lmn0 lmn1 out- out+ rx/sda tx/scl int ws ms sd sck scl sda pclkout dout(0:27) cds int rx/sda tx/scl lock in+ 1.8v in- ws sd sck dout28/mclk 4.99ki 4.99ki 45.3ki 45.3ki 49.9ki 49.9ki ws sd sck mclk pclk hsync rgb vsync to peripherals display max9850 max9260 MAX9259 lflt lflt www..net
gigabit multimedia serial link with spread spectrum and full-duplex control channel MAX9259/max9260 50 _____________________________________________________________________________________ package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: cmos package type package code outline no. land pattern no. 56 tqfn-ep t5688+2 21-0135 90-0046 64 tqfp-ep c64e+10 21-0084 90-0329 www..net
gigabit multimedia serial link with spread -spectrum and full-duplex control channel MAX9259/max9260 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 51 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 9/09 initial release 1 7/10 added clarification of fault thresholds and updated pin description table 3, 4, 8, 11, 12, 13, 15, 16, 17, 25, 28, 33, 39, 44, 48 2 11/10 added tqfn package to ordering information, absolute maximum ratings , pin configurations , pin description , and package information 1, 2, 10, 11, 50 3 1/11 added patent pending to features 1 www..net

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